Lithography techniques are key techniques in the manufacturing of integrated circuits. In a lithograph process, a photo resist is first applied on a wafer, a mask containing patterns of the desirable features is then placed over the wafer, the photo resist is then exposed to light, wherein due to the patterns on the mask, some portions of the photo resist are exposed to light, and some portions are not. The photo resist is then developed, with the exposed (or unexposed) portions removed. The patterns on the mask are thus transferred to the photo resist.
Due to the use of light in the exposure of the photo resist, when two devices on the wafer are too close to each other, optical proximity effects occur. Optical proximity effects are due to light diffraction and interference between closely spaced features, resulting in the widths of lines in the lithographic image being affected by other nearby features.
The proximity effects affect the process control in gate formation, which in turn results in endcap problems. FIG. 1 illustrates a conventional layout comprising two metal-oxide-semiconductor (MOS) devices. Gate 102 and active region 106 form a first MOS device 108. Gate 104 and active region 107 form a second MOS device 105. Gates 102 and 104 have endcaps 109 and 111 extending beyond active regions 106 and 107, respectively. Due to the micro-loading and/or optical proximity effects, endcaps 109 and 111 may be longer or shorter than designed. When endcaps 109 and 111 are longer than designed, gates 102 and 104 may be shorted, causing device failure. Conversely, problems may also occur if endcaps 109 and 111 are shorter than designed (referred to as line-end shortening), as shown in FIG. 2. If endcap 109 or 111 is recessed into active region 106 or 107, they cannot effectively control and turn off the channels of the respective MOS devices 108 and 105. As a consequence, significant leakage currents may exist between the source and drain of devices 108 and 105.
To solve the above-discussed problem, in the formation of the gates, two cut processes were used. Referring to FIG. 3, active regions 202 and 204 are formed close to each other. Gate strips 206 and 208 are first formed by blanket forming a gate electrode layer, and performing a first cut. Gate strips 206 and 208 extend all the way from over active region 202 to over active region 204. Next, a mask is made to cover active regions 202 and 204, and the portions of gate strips 206 and 208 directly over active regions 202 and 204. Opening 210 is formed in the mask to expose portions of gate strips 206 and 208. A second cut is performed to remove the portions of gate strips 206 and 208 exposed through opening 210. Advantageously, at the time the second cut is started, there is no exposed line end, and hence the line-end shortening problem is substantially eliminated.
The solution provided in FIG. 3, however, only applies if the gates over active region 202 and the gates over active region 204 have a same pitch. If different pitches are adopted, as shown in FIG. 4, the above-discussed solution is no longer usable. FIG. 4 illustrates a case, in which the pitch P of the gates over active region 202 is different from the pitch P′ of the gates over active region 204. In this case, gate electrode 206 extends from over active region 202 to over active region 204, while gate strips 230 and 232 cannot be aligned to form a single gate strip. As a result, endcaps 220 and 222 are exposed before the second cut is conducted. In the second cut, endcaps 220 and 222 will be etched more than the gates formed from gate strip 206, and hence the line-end shortening problem may occur. A solution is thus needed.